HBBR Assembler Reference

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Detailed Description

HBBR Assembler reference

Introduction

HBBRASM is an ARM ^(R) assembler language that can be assembled in-line (in BASIC code).

Assembly Language

HBBRASM supports ARM ^(R) UAL (Unified Assembler Language ) syntax.

ARM Assembly Language Reference

Assembler Line Syntax
Conditional Excecution Code
Addressing Mode Code
Exceptions
PSR Program Status Register

Assembler Line Syntax

{label} {instruction|pseudo-instruction|directive} {;comment}

label - follows identifier rules and ends with ':' instruction - assembler instruction op code pseudo-instruction - assembler pseudo-instruction op code directive - assembler directive comment - comment text following ;

Conditional Excecution Code

EQ eq - EQual
NE ne - Not Equal
CS cs HS hs - Higher or Same, Carry Set
CC cc LO lo - C clear or LOwer
MI mi - MIust (negative)
PL pl - PLus positive
VS vs - oVerflow Set
VC vc - oVerflow Clear
HI hi - HIgher
LS ls - LeSs
GE ge - Greater or Equal
LT lt - Less Then
GT gt - Greater Then
LE le - Less or Equal
AL al - ALways

Addressing Mode Code

IA ia - Increment After
IB ib - Increment Before
DA da - Decrement After
DB db - Decrement Before

Exceptions

Data Abort

PSR Program Status Register

PSR fields and bits

    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
    N Z C V - - - - - - - - - - - - - - - - - - - - I F T [ Mode  ]
    [ flags field ] [status field ] [exten. field ] [control field]

Flags field
N - Negative bit 31
Z - Zero bit 30
C - Carry bit 29
V - Overflow bit 28

Control field
I - IRQ Disable bit 7
F - FIQ Disable bit 6
T - Thumb State bit 5
M - Mode bits 0-4

Current Program Status Register CPSR \n

Saved Program Status Register SPSR \n

Predefined Registers

r0 R0 a1 A1 - register 0 argument 1
r1 R1 a2 A2 - register 1 argument 2
r2 R2 a3 A3 - register 2 argument 3
r3 R3 a4 A4 - register 3 argument 4
r4 R4 v1 V1 - register 4 variable 1
r5 R5 v2 V2 - register 5 variable 2
r6 R6 v3 V3 - register 6 variable 3
r7 R7 v4 V4 - register 7 variable 4
r8 R8 v5 V5 - register 8 variable 5
r9 R9 v6 V6 - register 9 variable 6
r10 R10 v7 V7 sb SB - register 10 variable 7 static base
r11 R11 v8 V8 fp FP - register 11 variable 8 frame pointer
r12 R12 ip IP - register 12 intra-procedure
r13 R13 sp SP - register 13 stack poiner
r14 R14 lr LR - register 14 link register
r15 R15 pc PC - register 15 program counter

Instructions

Summary
Memory
Data processing
Multiply
Load and Store Multiple
Branch
Miscellaneous
Pseudo-instructions

Summary

Alphabetical list of instructions

Supported instructions in alphabetical order

ADC
ADD
AND
B
BL
BIC
CMN
CMP
EOR
LDM
LDMIA
LDMIB
LDMDA
LDMDB
LDR
LDRB
LDRSB
LDRH
LDRSH
MLA
MRS
MSR
MUL
MOV
MVN
ORR
POP
PUSH
RSB
RSC
SBC
SMLAL
SMULL
STM
STMIA
STMIB
STMDA
STMDB
STR
STRB
STRSB
STRH
STRSH
SUB
SWP
SWPB
SVC
SWI
TEQ
TST
UMLAL
UMULL

Memory

Immediate Offset
Memory Access Instructions

Data processing

Operand2
Data Processing instructions

Multiply

MLA MLAS instruction
MUL MULS instruction
SMLAL SMLALS instruction
SMULL SMULLS instruction
UMLAL UMLALS instruction
UMULL UMULLS instruction

Load and Store Multiple

Register list
Load and Store Multiple Instructions
Push Pop Instructions

Branch

B BL instruction

Miscellaneous

SWP SWPB instruction
SVC instruction
SWI instruction
MRS instruction
MSR instruction

Pseudo-instructions

LDR pseudo-instruction

Directives

Miscellaneous

Miscellaneous

AREA directive

Labels

Local labels start with a number followed by the optional name

Syntax

number name

        1
        12345
        01loop

Operand2

Syntax

#8bit_immediate

Rm, shiftcode #immediate

Rm, shiftcode Rs

Shift codes

        ASR,  LSL,  LSR,  ROR

Immediate Offset

Syntax

#immediate_offset

Register list

Syntax

List

{ Register | register_range }

register

R0 | R1 | R2 | R3 | R4 | R5 | R6 | R7 | R8 | R9 | R10 | R11 | R12 | R13 | R14 | R15 | SB | FP | IP | SP | LR | PC


register_range

register - register

Example

        {}
        {R0}
        {R0-R15}
        {R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15}
        {SB, FP, IP, SP, LR, PC}
        {R0-R3, R4-R7, R10-R15}
        {R0-R8, SB, FP, IP, SP, LR, PC}

Memory Access Instructions

Opcodes OP - word, byte, signed byte, half word, signed half word

        LDR,  LDRB,  LDRSB,  LDRH,  LDRSH
        STR,  STRB,  STRSB,  STRH,  STRSH

Syntax

Immediate Offset

OP{condcode} Rd, [ Rn,#offset ]

Pre-index

OP{condcode} Rd, [ Rn,#offset ]!

Post-index

OP{condcode} Rd, [ Rn ],#offset

Opcodes OPD - double word

        LDRD
        STRD

Syntax

Immediate Offset

OPD{condcode} Rd, Rd2, [ Rn,#offset ]

Pre-index

OPD{condcode} Rd, Rd2, [ Rn,#offset ]!

Post-index

OPD{condcode} Rd, Rd2, [ Rn ],#offset

Parameters:

	condcode	see Conditional Excecution Code
	offset	see Immediate Offset

Syntax variants for OP - word, byte, signed byte, half word, signed half word

Immediate Offset

OP{condcode} Rd, [ Rn,#offset ]
OP{condcode} Rd, [ Rn ]

Pre-index

OP{condcode} Rd, [ Rn,#offset ]!
OP{condcode} Rd, [ Rn ]!

Post-index

OP{condcode} Rd, [ Rn ],#offset

Syntax variants for OPD - double word

Immediate Offset

OP{condcode} Rd, Rd2, [ Rn,#offset ]
OP{condcode} Rd, Rd2, [ Rn ]

Pre-index

OP{condcode} Rd, Rd2, [ Rn,#offset ]!
OP{condcode} Rd, Rd2, [ Rn ]!

Post-index

OP{condcode} Rd, Rd2, [ Rn ],#offset

Instruction set

ARM

Example

        LDR  R2, [R1]
        LDR  R2, [R1,#12]
        STR  R0, [R3,#20]!
        STR  R3, [R4],#40

Load and Store Multiple Instructions

Opcodes

        LDM, LDMIA, LDMIB, LDMDA, LDMDB
        STM, STMIA, STMIB, STMDA, STMDB

Syntax

OP{addressing_mode }{condcode } Rn { ! }, register_list { ^ }

Parameters:

	addressing_mode	see Addressing Mode Code
	condcode	see Conditional Excecution Code
	register_list	see Register list

Syntax variants

LDM{addressing_mode }{condcode } Rn { ! } , register_list
LDM{addressing_mode }{condcode } Rn , register_list_excluding_PC ^
LDM{addressing_mode }{condcode } Rn { ! } , register_list_including_PC ^
STM{addressing_mode }{condcode } Rn { ! } , register_list
STM{addressing_mode }{condcode } Rn , register_list ^

Note:

Instruction set

ARM

Exceptions

Data Abort

Example

        LDM    SP,{R0-R14}^
        LDMDB  R0,{R0-R15}
        STMBIA SP,{R1,R2
        STMDB  R13!,{R1,R4-R8}

Push Pop Instructions

Opcodes

        PUSH
        POP

Syntax

OP{condcode } register_list

Parameters:

	condcode	see Conditional Excecution Code
	register_list	see Register list

Syntax variants

PUSH{condcode } register_list
POP{condcode } register_list

Note:

PUSH register_list is synonym for STMDB R13!, register_list
POP register_list is synonym for LDMIA R13!, register_list
see Load and Store Multiple Instructions

Instruction set

ARM

Exceptions

Data Abort

Example

        PUSH {R0-R15}
        PUSH {R1.R2,R8}
        PUSH {FP}
        POP  {R0,R1,R2,R3}
        POP  {R0,R1,R2,R3,PC}

Data Processing instructions

Opcodes

        AND,  EOR,  SUB,  RSB,  ADD,  ADC,  SBC,  RSC,  TST,  TEQ,  CMP,  CMN,  ORR,  MOV,  BIC,  MVN
        ANDS, EORS, SUBS, RSBS, ADDS, ADCS, SBCS, RSCS, TSTS, TEQS, CMPS, CMNS, ORRS, MOVS, BICS, MVNS

Syntax

OP{condcode} Rd, Rn,Operand2

Parameters:

	condcode	see Conditional Excecution Code
	Operand2	see Operand2

Syntax variants

OP{condcode} Rn, #8bit_immediate
OP{condcode} Rd, Rn, #8bit_immediate
OP{condcode} Rd, Rn, Rm
OP{condcode} Rn, Rm
OP{condcode} Rd, Rn, Rm, shiftcode #immediate
OP{condcode} Rn, Rm, shiftcode #immediate
OP{condcode} Rd, Rn, Rm, shiftcode Rs
OP{condcode} Rn, Rm, shiftcode Rs

Note:

For opcodes TST, TEQ, CMP and CMN S bit is added be the assembler, bahavior is the same as TSTS, TEQS, CMPS and CMNS .

Instruction set

ARM

Example

        ADD  R0, R1, R2
        SUBS R4, R7, R8
        SBCS R3, R5, FP
        MOV      R0, R1
        MOVN R0, R1
        MOVS LR, LR, LSL R5

B BL instruction

Branch , Branch and Link

Opcodes

        B BL

Syntax

B {condcode} #immediate
BL {condcode} #immediate

Parameters:

	condcode	see Conditional Excecution Code
	immediate	User specified 24 bit signed immediate value represeting target address relative offset from current PC. The target address is calculated by: Sing extending immediate to 30 bits Shifting left by 2 bit positions - ( makes 32 bit singned number) Adding current PC value to form absolute address. Current PC value is branch address plus 8.

Instruction set

ARM

Note:

The B and BL can branch range is almost +/- 32 MB relative to the PC . When calculating the immediate use address of the branch + 8 as specified by the PC.

Example

        B #0
        BL #0

SVC instruction

SuperVisor Call through an exception

Opcodes

        SVC

Syntax

SVC {condcode} #immediate

Parameters:

	condcode	see Conditional Excecution Code
	immediate	User specified immediate value ignored by the processor. 24 bit when assembling ARM instruction set

Instruction set

ARM

Note:

SVC instruction is a renamed SWI.

Example

        SVC #1

SWI instruction

SWI has been renamed to SVC see SVC instruction

Opcodes

        SWI

Note:

Accepted for compatibility.

MUL MULS instruction

Multiply

Multiply 32 bit signed or unsigned values in registers Rm and Rs
Store least significant 32 bits of the result in the destination register Rd.

Opcodes

        MUL
        MULS

Syntax

MUL {condcode} Rd, Rm, Rs
MULS {condcode} Rd, Rm, Rs

Parameters:

condcode

see Conditional Excecution Code

Instruction set

ARM

Example

        MUL  R0,R1,R2
        MULS R3,R4,R5

MLA MLAS instruction

Multiply Accumulate

Multiply 32 bit signed or unsigned values in registers Rm and Rs add value in the register Rn.
Store least significant 32 bits of the result in the destination register Rd.

Opcodes

        MLA
        MLAS

Syntax

MLA {condcode} Rd, Rm, Rs, Rn
MLAS {condcode} Rd, Rm, Rs, Rn

Parameters:

condcode

see Conditional Excecution Code

Instruction set

ARM

Example

        MLA  R0,R1,R2,R4
        MLAS R5,R6,R7,R8

SMLAL SMLALS instruction

Signed Multiply Accumulate Long

Multiply 32 bit signed values in registers Rm and Rs add value in the register RdLo and RdHi.
Store least significant 32 bits of the result in the destination register RdLo.
Store most significant 32 bits of the result in the destination register RdHi.

Opcodes

        SMLAL
        SMLALS

Syntax

SMLAL {condcode} RdLo, RdHi, Rm, Rs
SMLALS {condcode} RdLo, RdHi Rm, Rs

Parameters:

condcode

see Conditional Excecution Code

Instruction set

ARM

Example

        SMLAL  R0,R1,R2,R4
        SMLALS R5,R6,R7,R8

SMULL SMULLS instruction

Signed Multiply Long

Multiply 32 bit signed values in registers Rm and Rs.
Store least significant 32 bits of the result in the destination register RdLo.
Store most significant 32 bits of the result in the destination register RdHi.

Opcodes

        SMULL
        SMULLS

Syntax

SMULL {condcode} RdLo, RdHi, Rm, Rs
SMULLS {condcode} RdLo, RdHi Rm, Rs

Parameters:

condcode

see Conditional Excecution Code

Instruction set

ARM

Example

        SMULL  R0,R1,R2,R4
        SMULLS R5,R6,R7,R8

UMLAL UMLALS instruction

Unsigned Multiply Accumulate Long

Multiply 32 bit unsigned values in registers Rm and Rs add value in the register RdLo and RdHi.
Store least significant 32 bits of the result in the destination register RdLo.
Store most significant 32 bits of the result in the destination register RdHi.

Opcodes

        UMLAL
        UMLALS

Syntax

UMLAL {condcode} RdLo, RdHi, Rm, Rs
UMLALS {condcode} RdLo, RdHi Rm, Rs

Parameters:

condcode

see Conditional Excecution Code

Instruction set

ARM

Example

        UMLAL  R0,R1,R2,R4
        UMLALS R5,R6,R7,R8

UMULL UMULLS instruction

Unsigned Multiply Long

Multiply 32 bit unsigned values in registers Rm and Rs.
Store least significant 32 bits of the result in the destination register RdLo.
Store most significant 32 bits of the result in the destination register RdHi.

Opcodes

        UMULL
        UMULLS

Syntax

UMULL {condcode} RdLo, RdHi, Rm, Rs
UMULLS {condcode} RdLo, RdHi Rm, Rs

Parameters:

condcode

see Conditional Excecution Code

Instruction set

ARM

Example

        UMULL  R0,R1,R2,R4
        UMULLS R5,R6,R7,R8

SWP SWPB instruction

Swap

Store value in register Rm in memory location addressed by register Rn.
Load Rd with the original value in memory location addressed by the register Rn.
When both Rm and Rd specify the same register then value in Rm is swapped with the
value in memory location addressed by register Rn.
Swap is an atomic operation that can be used to implement semaphores.

SWP swaps words while SWPB swaps bytes.

Opcodes

        SWP
        SWPB

Syntax

SWP {condcode} Rd, Rm, [ Rn ]
SWPB {condcode} Rd, Rm, [ Rn ]

Parameters:

condcode

see Conditional Excecution Code

Instruction set

ARM

Exceptions

Data Abort

Example

        SWP  R0,R0,[R1]
        SWPB R2,R3,[R4]

MRS instruction

Move PSR to register.

Move either the CPSR or the SPSR of the current mode to register Rd.

Opcodes

        MRS

Syntax

MRS {condcode} Rd, CPSR
MRS {condcode} Rd, SPSR

Parameters:

condcode

see Conditional Excecution Code see Current Program Status Register CPSR see Saved Program Status Register SPSR

Instruction set

ARM

Exceptions

Example

        MRS  R0,CPSR
        MRS  R0,SPSR

MSR instruction

Load constant or register into PSR.

Load either the CPSR or the SPSR with constant or value in register Rm.
Flags will be set based on selected fields.

Opcodes

        MRS

Syntax

MRS {condcode} CPSR_flags, Rm
MRS {condcode} CPSR_flags, #immediate
MRS {condcode} SPSR_flags, Rm
MRS {condcode} SPSR_flags, #immediate

Parameters:

condcode

see Conditional Excecution Code see Current Program Status Register CPSR see Saved Program Status Register SPSR

Field flags

Use any combination of [f s x c] to set flags in the corresponding field
See PSR Program Status Register for more details

c - control field sets PSR bits [7:0]
x - extension field sets PSR bits [15:8]
s - status field sets PSR bits [23:16]
f - flags field sets PSR bits [31:24]

Instruction set

ARM

Exceptions

Example

        MSR  CPSR_fsxc, #0
        MSR  SPSR_fsxc, [R0]

MOV32 pseudo-instruction

Load 32 bit constant or symbol address into destination register.

Syntax

MOV32 {condcode} Rd, constant
MOV32 {condcode} Rd, symbol

Note:

Always generates a pair of MOV, MOVT 32 bit instructions.
When used to load address then code is not position independent.
Desitination register can not be SP or PC.

Example

//      MOV32 R0, 0
//      

LDR pseudo-instruction

Load 32 bit constant or symbol address into destination register.

Syntax

LDR {condcode} Rd, = constant
LDR {condcode} Rd, = symbol

Note:

Generates MOV or MVN instrunction if the constant or address is in the range.
When used to load address then code is not position independent.
Can only load address of symbols with absoulte values (limitation).

Example

        LDR R0, =1

AREA directive

Syntax

AREA name {, attribute }

Attributes

Note:

Directive is not available in in-line assembler.

Example

  AREA .text